ATIXI Compute / Research program
Build a more efficient foundation for intelligent computing.
We are researching how next-generation CPU architecture and intelligent software scheduling could make AI-agent workloads more efficient, secure and accessible.
Software research
ATIXI Runtime
CPU-oriented agent orchestration and intelligent task scheduling.
Early software proof of concept
Processor research
ATIXI X1 CPU
A proposed RISC-V-based processor initiative for AI-centric computing.
Architecture concept
Technical publications
Research, openly shared.
Vision, architecture and benchmark methodology.
Program status
Evidence before claims.
Follow the scope, milestones and limits of our research.
Our approach
Intelligent by design. Human by nature.
Measure first. Prototype carefully. Publish responsibly.
Company profile
Why. What. How.
WHY WE EXIST
AI should deliver more value with fewer resources.
AI infrastructure is growing more complex and expensive. We believe its next evolution must prioritize measurable efficiency, openness in evaluation and human benefit.
WHAT WE BUILD
A coordinated hardware–software research program.
ATIXI Runtime explores CPU-oriented agent orchestration. ATIXI X1 is our proposed RISC-V-based processor initiative for future AI-centric computing.
HOW WE WORK
Measure first. Prototype carefully. Publish responsibly.
We begin with reproducible software experiments, evaluate RISC-V on FPGA, and pursue custom silicon only when evidence supports architectural advantages.
Research areas
One ambition. Two interconnected projects.
Research area
ATIXI Runtime
Initial task scheduling proof of concept and microbenchmark tools. Planned work includes workload-aware routing, isolation, telemetry and model inference adapters.
Status: early software proof of concept
Research area
ATIXI X1 CPU
A proposed future processor research program using RISC-V evaluation, system simulation, FPGA prototypes and architecture-level performance studies.
Status: architecture concept — no fabricated CPU
Research area
ATIXI Research
Publish defined workloads, measurements, risks and engineering decisions. Our proposed performance targets are goals, not demonstrated results.
Status: methodology and papers available
Technical publications
Our research papers
Open concept papers for developers, researchers and potential partners. These documents are research drafts, not peer-reviewed findings.
Technical paper 1
01 · Why, What, How
The problem we want to solve, our company mission and scientific approach.
Technical paper 2
02 · X1 Architecture
RISC-V starting point, prototype gates, FPGA bring-up and engineering risks.
Technical paper 3
03 · Benchmark Method
Reproducibility standards, baseline selection and measurement criteria.
Research status
Evidence before claims.
Our software scheduler and illustrative logic unit are prototypes. ATIXI X1 has not been fabricated or validated as a commercial CPU. We have not demonstrated superiority over NVIDIA, AMD or Intel. We will publish measured results when reproducible evidence exists.
Research draft
ATIXI Compute — Why, What, How
Technical concept paper 01 · Research draft · 22 October 2026
Why
AI infrastructure must become more efficient, accountable, accessible and adaptable. Today's AI systems combine intensive model inference with diverse, latency-sensitive CPU tasks. Organizations need verifiable cost, energy and security improvements rather than unsupported performance promises.
What
ATIXI Compute is a proposed fabless semiconductor R&D initiative. Its two coordinated projects are ATIXI Runtime (software orchestration research) and ATIXI X1 (a future RISC-V-based agent-oriented processor). At publication, neither X1 silicon nor a complete X1 processor exists.
How
Build an openly testable runtime POC; measure realistic agent workloads; investigate RISC-V FPGA prototypes; only then prioritize silicon design features and manufacturing feasibility. Distinguish hypothesis from tested measurements and publish repeatable methods.
Research questions
Can CPU scheduling and memory prioritization reduce agent workflow latency? Can reliable workload isolation be achieved without excessive overhead? Does runtime-driven architectural co-design deliver meaningful cost or energy advantages over mature processors?
Disclosure
The included prototype demonstrates scheduler behavior and toy workloads. It does not demonstrate hardware performance, independent benchmarks, or a commercially viable CPU. NVIDIA, Intel and AMD are competitors for comparison, not ATIXI partners.
Research draft
ATIXI X1 — Architecture and FPGA Research Note
Technical concept paper 02 · Research draft · 22 October 2026
Proposed architecture
Initial full-system evaluation targets a licensed, existing 64-bit RISC-V core implementing suitable privileged modes, MMU and relevant standard extensions. The research program evaluates memory hierarchy, scheduling telemetry, interrupt behavior, context transitions and secure agent isolation. A new custom microarchitecture is conditional on benchmark findings.
Distinguishing RTL from processor
A small x1_alu.sv combinational unit is provided as a learning/test scaffold only. A complete CPU also requires instruction fetch/decode, registers, control, exceptions, caches and memory interconnect, among other systems.
Experimental stages
(1) CPU and SoC simulation; (2) verification against ISA specifications; (3) FPGA integration with UART and memory; (4) Linux bring-up; (5) runtime workload replay; (6) energy and throughput comparison; (7) design review and potential silicon feasibility study.
Risks
Complex engineering, foundry costs, IP and tool licensing, power integrity, verification burden, compiler maturity, and competitiveness against leading incumbents. No tape-out schedule is committed.
Relevant technical references
Research draft
ATIXI Runtime — Measurement and Reproducibility Method
Technical concept paper 03 · Research draft · 22 October 2026
Research design
Test orchestration workloads separately from model inference. Define public workload traces; fix software and hardware versions; record raw results; report distributions and uncertainty. Apply both latency and system efficiency measures.
Current deliverable
The Python implementation compares sequential and thread-based schedules of hash, JSON, and simulated wait tasks. It verifies task result integrity. Threaded wait improvements are expected to reflect overlapped sleeps and cannot be interpreted as CPU benchmark results.
Next instrumentation milestones
Collect CPU cycles, instructions, cache misses, context switches, p95/p99 latency, memory footprint, wall energy, and isolated tenant overhead. Compare x86, Arm and RISC-V using matched workload configuration. Track model inference costs separately.
Publication policy
Every external efficiency or speed comparison must include hardware identifiers, compiler/runtime versions, workload inputs, sample counts, variance and raw data. Proposed target numbers are hypotheses, never marketed as achieved results.